1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an internal circuit that is in contact with an external element through an input/output pad.
2. Description of the Related Art
A semiconductor integrated circuit, which is fabricated using complementary metal-oxide-semiconductor (CMOS) technology, is susceptibly to the effects caused by a high voltage flowing from static electricity or electrostatic discharge (ESD) that is generated due to contact with a human body or the like. The ESD phenomenon easily causes the break of a thin insulating layer formed in the integrated circuit or the malfunction of an integrated circuit chip, e.g., a channel short circuiting, because a high voltage is applied to the integrated circuit chip at once. When static electricity generated from a regulated power supply contacts a lead of a semiconductor product, it is input as an impulse type signal to the semiconductor product through the lead. The input static electricity passes through a path from the lead to a ground line, which provides the minimum product of electric potential and time, and is discharged from the semiconductor product while inflicting damage on the semiconductor product. In most cases, a circuit is designed to lead a path of damage due to static electricity to an ESD protection circuit (refer to U.S. Pat. No. 6,198,136 B1). However, in spite of such circuit design, there have been many cases where semiconductor products, especially, internal circuits, are seriously affected by static electricity.
FIG. 1 is a circuit diagram of a conventional semiconductor device 10 having ESD protection circuits.
Referring to FIG. 1, the conventional semiconductor device 10 includes ESD protection circuits 24, which are between a power supply line 12 to which an external voltage Vcc is applied and a ground line (Gnd) 14. The ESD protection circuits 24 are connected to two diodes D1 and D2, respectively, which are branched from an input/output pad 20.
In the conventional semiconductor device 10, if an electric potential is lower in a first path between a lead 32 and the ground line 14, which goes by way of an input/output signal line 22 and an internal circuit 30, than in a second path between the lead 32 and the ground line 14, which goes by way of the ESD protection circuit 24, and if a sink time, which is a time taken to discharge static electricity input from the lead 32 through the ground line 14, is shorter in the first path than in the second path, static electricity ends up passing through the input/output signal line 22 and the internal circuit 30. In this case, the internal circuit 30 is fatally damaged by the static electricity.